College of Engineering, Architecture and Technology, OSUIndependent Researcher
Jan. 2014 - May. 2015StillwaterRESEARCH ON GRAPHENE ELECTRONICS
--Studied about Graphene electronic properties and on methods to overcome the bandgap limitation.
--Detailed analysis of graphene transistors (GFETs), IV Characteristics.
--Researched on methodologies that are used in designing basic logic gates like inverters as well as other complex logic gates like mux, adders using GFETs.
--Designed computational models of mux, Decoder using Negative Differential Resistance property of Graphene.
--Discovered the need of studying Physical design and RTL Design methods of Electrical circuits/Systems in detail in order to design Graphene electronics, so went on to study and work on the subjects.
--Tools used: MATLAB VLSI CIRCUIT/PHYSICAL DESIGN
--Studied and Researched about multi-bit full adders and types of tree adders.
--Detailed analysis of Parasitic RLC, Delay, Noise Analysis, Clock characteristics; Static timing analysis of tree adders
--Designed 32-bit SRAM memory block, 32-bit pipelined full adder with low power, small area tradeoffs using Cadence, Synopsys in UNIX environment . -- Script development to implement the VLSI design flows; Synthesis, floorplan, Place, Clock tree synthesis, route, formal verification, Static timing analysis, Physical Verification (LVS, DRC).
--Tools used: MAGIC, Cadence , Synopsys, Tcl, UNIX. ASIC/RTL DESIGN
--Defined, designed and verified the ASIC model/ RTL Design of 32-bit CPU, using Verilog on Modelsim Quartus II and Xilinx ISE. --Studied about modeling memory elements, instruction set design, pipelining, Hazards, Exceptions, integer and floating point units etc., for a modern computer design. --Implemented structural and behavioral design of modules like ALU, Register set, controller, 3-4-5 stage pipelined CPU with small area and low power methods.
--RTL synthesis, development of testbench for each module, validation of the design, debug.
Tools used: Verilog, Modelsim, Xilinx ISE.