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Work Background
Technical Lead and Senior Engineering Manager - Platform Services
CelonaTechnical Lead and Senior Engineering Manager - Platform Services
Feb. 2024San Francisco Bay Area
Technical Lead and Engineering Manager - Platform Services
CelonaTechnical Lead and Engineering Manager - Platform Services
Jan. 2022 - Feb. 2024San Francisco Bay Area
Member Of Technical Staff - Platform Services
CelonaMember Of Technical Staff - Platform Services
Sep. 2019 - Feb. 2022San Francisco Bay Area
Member of Technical Staff
NutanixMember of Technical Staff
Sep. 2016 - Sep. 2019San Jose, CaliforniaMember of Disaster Recovery team
Member of Technical Staff
Nutanix (PernixData)Member of Technical Staff
Jul. 2015 - Sep. 2016San Jose, CaliforniaMember of storage protocols team. My contributions include - implementation of VAAI capabilities - ALUA support for FC and iSCSI platforms - implementation of stats framework to track performance of the SCSI stack
Software Engineer (Solaris Core Kernel)
Oracle Inc.Software Engineer (Solaris Core Kernel)
Feb. 2013 - Jul. 2015San Francisco Bay AreaMember of the Solaris Core Kernel Team. - Triage Engineer for Syscalls area - Working on making the Solaris Kernel highly scalable from multi-core to many-core systems - Current Project: Event notification mechanisms in Solaris using Event Ports - Past Projects: NUMA Aware Locking Techniques (Patent pending)
Graduate Research Assistant
Carnegie Mellon UniversityGraduate Research Assistant
Aug. 2012 - Jan. 2013Greater Pittsburgh AreaWorking at the Quality of Life Technology Center on a Kinect based project. The project aims to complete a system that would help people working in a desktop work environment to avoid injuries like carpal tunnel syndrome.
Software Engineering Intern
QualcommSoftware Engineering Intern
May. 2012 - Aug. 2012Greater San Diego AreaWorked on the QNX Team of the QCT (Qualcomm CDMA Technologies) division. The team is responsible for providing the firmware for RIM's QNX RTOS to run on Snapdrangon processors of Qualcomm. - Wrote a library that attaches two interrupt handlers to the kernel on boot-up, checks for L1 and L2 cache parity errors, logs the errors and updates clock drivers to avoid further errors. - Completed performance analysis of device driver APIs for Power Management IC (PMIC), SPI and SMMU.
Student Intern
National Thermal Power Corporation LtdStudent Intern
May. 2009 - Jul. 2009In-plant training and completion of a mini-project Learning Outcomes - Overview of the complete power generation process - Detailed learning on the instrumentation at various installations in the plant - Detailed learning on Distributed Digital Control (DDC) systems - Designed and implemented control logic in Pro-Control DDC for tank level control with automatic switching of redundant pumps
Student Intern
Yokogawa India LtdStudent Intern
Apr. 2009 - May. 2009Certificate Course on Distributed Control Systems (DCS) Fundamentals, Engineering and Maintenance Learning Outcomes - Architecture of CENTUM CS-3000 R3 - Communication protocols and Object Linking and embedding (OLE) for Process Control - Implementation of Ladder Logic in CENTUM CS-3000 R3 - Architecture, features and logic implementation in ProSafe-RS PLC
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