Feb. 2019Zapopan, Jalisco, México- Focus area : CPU Power Management & Reset.
- Functional validation in Pre-Silicon and Post-Silicon at system and internal component level.
- Debug failures cross HW and FW to solve complex scenarios and interacting with architecture, design and pre-si teams to enabling robust design fixes.
- Creation, definition and development test strategies and test plans driving detailed technical readiness for all debug enabling solutions for CPU products identifying gaps/risks and work with stakeholders to
resolve them.
- Test content development (Python).
Intel CorporationPost-Si and Emulatio Validation Engineer
Jun. 2012 - Jan. 2019Guadalajara- Functional validation against component specifications at internal level.
- Focus area : Power Management & Resets.
- Definition and Development of test cases and test content (Python).
- Test planning execution monitoring and reporting test results.
- Debug for Power Management and reset flows.
- Test and debug the emulation/FPGA model and collaterals.
Instituto de Investigaciones EléctricasFirmware and Electronic design engineer
Apr. 2008 - Jun. 2012Cuernavaca, Morelos- Firmware development for device control and communications solutions.
- Software development for automation LabVIE.
- Design of digital circuits for measurement systems.
- Design of analog circuits for RF systems.
Dextra TechnologiesSoftware engineer
Aug. 2008 - Jan. 2009Software development focused on embedded systems.
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