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Work Background
Intel CorporationTech. Lead & Customer engagement (FPGA & Emulation)
Jan. 2018San Francisco Bay Area• Led hands-on bring-up of VCS/FPGA/ZSE Xeon Emulation models, conducting functional validation of reset flows involving firmware and software stacks. Personally identified and debugged RTL, BIOS, and ROM issues using lab tools. • Directly engaged with external customers on interop projects, enabling new security flows on Silicon and HAPS FPGAs. Used tools like PCIe Analyzer and Lauterbach Trace32 to resolve issues and successfully cut time-to-market by two quarters. • Executed the HAPS FPGA bring-up of Intel Data Center GPU SoC for AI and HPC applications, ensuring proper functionality and meeting performance benchmarks for US Federal Projects. • Developed and validated Server SoC HAPS FPGA prototypes focused on CXL/PCIe IP by handling timing constraints, synthesis, routing, and creating debug scripts for key interfaces like JTAG, PCIe, UART, I2C, SPI. • Designed and implemented a FPGA Cloud Usage that boosted scalability and model convergence by 25%, significantly improving adoption rates across customer platforms. • Actively performed synthetic validation of IPs such as Power Management, Secure Boot, and DMA before release, ensuring system stability and readiness for customer deployment. • Led a multi-disciplinary team of 10+ engineers and technicians, managing the transition to Xilinx HAPS FPGAs for critical SoC development. Coordinated hands-on integration tasks across geographies, ensuring alignment with SoC milestones. • Worked closely with program managers and device integration teams to drive milestones for DSPs, sensors, and RF systems, including use cases for 3G UMTS, 4G LTE, GPS, Wi-Fi, and Bluetooth in complex embedded environments. • Chaired two cross-organizational forums, facilitating collaboration between teams (CAD, IPs, Validation, SW) and driving FPGA-based use cases and validation flows, with 15+ active participants from different departments • Consistently recognized as a top performer, receiving multiple divisional and cross-department awards
Intel CorporationTech. Lead, Data Center Software & Solutions Group
Jan. 2016 - Dec. 2017California, United States• Led a task-force of 4 engineers in the hands-on development of accelerator IP targeting Big Data workloads on Data Center products. This involved implementing the Xeon+FPGA flow, where I personally oversaw the simulation and bring-up of custom IP cores for cloud deployment at a leading CSP customer. • Directly collaborated with the Data Center team to optimize platform acceleration for Big Data, focusing on improving system throughput and performance for real-time analytics. • Co-developed a Gzip compression IP as a hardware accelerator, actively involved in RTL simulation, debugging, and FPGA validation. This IP was successfully deployed by a major CSP to enhance data compression and processing efficiency. • Executed hands-on RTL simulation and FPGA bring-up for a Java Byte-code Processor, designed specifically for Big Data applications. This included managing the end-to-end development of the processor, validating its integration into the FPGA-based environment to accelerate data center workloads.
Intel LabsResearch Scientist
Jan. 2014 - Dec. 2015San Francisco Bay AreaMicro Architecture Lab • Core member of ADR Team (Advanced Design Research) • Investigate the feasibility of applying concepts to potential inventions and products typically 7+ years prior to landing on a product roadmap. • Power/area/performance driven architecture and microarchitecture optimization of CPU, GPU, interconnect fabric and SoC platform architecture. • FPGA emulation and prototyping of key design IP and SoC
Infineon Mobile CommunicationsStaff Engineer
Jan. 2010 - Dec. 2013San Francisco Bay Area• Key member of 5+ commercially successful wireless chip designs • Pro-active staff member of Architecture and Emulation Team focusing on Bluetooth Core • Lead SoC FPGA Development for Intel’s first Connectivity (BT/WLAN/FM/GNSS) • Managed a complex portfolio of FPGA/Firmware release program • Test Plan Development and Execution, Pre Silicon FPGA/Firmware Development • Designed ROM Patching, External Memory I/F, PCM, USIM Controller, IC USB • Silicon Bring up/Characterization/Power/Coexistence etc.
Intel CorpSenior Engineer
Jan. 2006 - Dec. 2009• Working knowledge on the 4G, IEEE 802.16 WiMAX standards • Test Plan Development, Execution and Silicon Validation of WiMAX Products • Embedded Software Development for Intel WiMAX.
QualcommSystem Engineer
Jan. 2004 - Dec. 2005La Jolla, San Diego, California, United States• GSM GPRS EDGE System Integration, Field Tests, IOT, Regression • InterRAT and 3G WCDMA/HSDPA System Integration, IOT • Feature Integration & Systems Performance
Texas A&M UniversityAssistant Lecturer at Electrical Engineering and Computer Engineering
Jan. 2001 - Dec. 2004Texas, United States
TechnofourEngineer
Apr. 1999 - Dec. 2000• Designed Automated Vision and Inspection Systems, this vision and image processing system monitored a volumetric bottle filling station designed for the pharmaceutical industry • Designed mechatronics for dynamic check weighers, flaw and defect detection systems, NDT
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