Requests
0
Keep in touch with meI'm using Intch to connect with new people. Use this link to open chat with me via Intch app
Work Background
Analog DevicesSenior Engineer
Jun. 2024Bengaluru, Karnataka, IndiaWorking on the Formal Verification for Multi die SoC for AI applications: -> Complete end-to-end ownership for formal verification of the switch matrix of the SoC. -> Successfully deployed Sentence Transformer based simulation logs binning solution on ADI's HPC infrastructure to enable DV engineers across ADI to be able to do intelligent binning of 1000s of logs generated from the regression for faster debug cycles. -> Side Projects/ Achievements : * Got runners up position out of 24 teams in a Data Hackathon where we have to propose data monetization techniques for ADI. I proposed the idea of creating Data-as-a-service model on top of the SOC platform for PV inverters giving insights to customers by leveraging weather models for demand forecasting and smart management of solar inverters. Also proposed AI model for predicting latent faults for functional safety of PV inverters. * Got runners up position out of 9 teams in ML challenge across ADI to create an AI/ML based end-to- end solution for regression logs binning for faster debug of DV issues. The solution was very cost- effective and scalable also as it was designed to run on a CPU completely avoiding high cost of GPU infrastructure to run an AI based solution.
Samsung ElectronicsLead Engineer
Jun. 2023 - Jun. 2024Bengaluru, Karnataka, IndiaLeading the verification of Multimedia IPs for Samsung's flagship S series mobile phones: -> Led team to complete IP level verification of two NVGR IPs for Samsung's Flagship S Series phone within 7- month timeframe, collaborating with designers and architects to understand IP specifications. -> Developed completely reusable and scalable test bench infrastructure from scratch and performed complete coverage sign off of both IPs within required timeline. -> Strategized and executed detailed test plan through thorough analysis of specification documents and architecture understanding, ensuring comprehensive scenario coverage. -> Used Generative AI extensively to analyze C reference model and identified corner cases not included in test plan hence enhancing existing test plan. -> Used Generative AI to accelerate code development for test bench components. -> Implemented scalable and portable scoreboard, integrating C-based reference model with DPI-C interface, to ensure precise verification outcomes. -> Implemented data exchange mechanisms between C model and SV-UVM environment, utilizing queues and arrays for efficient data handling for score boarding. -> Facilitated effective communication with design engineers, assuming full responsibility for debugging and resolving failing scenarios.
STMicroelectronicsSenior Design Engineer
Nov. 2020 - May. 2023Project: Verification of Digital Blocks of Analog In-Memory Compute IP for AI/ ML Applications -> Utilized Python and PyTorch to generate vectors for Neural Processor verification, highlighting AI hardware verification skills. -> Performed Quantization-Aware Training to create 4-bit/ 4-bit (Features / Weights) precision models like ResNet-18, VGGNet which can be deployed on In-Memory Compute IP for Low Power AI applications. -> Crafted Python scripts to analyze and optimize power usage via register activity analysis.
Established an SV-UVM based transaction-level verification environment for digital blocks, ensuring scalability and reusability. -> Designed and implemented functional coverage, sequences, and scoreboards for key components, facilitating IP level reuse and aiding in debugging and specification refinement. -> Introduced a self-checking mechanism in the SOC environment, enhancing data verification accuracy. Project: SOC-level verification of Digital In-Memory Compute IP for AI/ ML Applications -> Transitioned the verification environment to the Palladium Z1 Emulation platform, maintaining portability between simulation and emulation. -> Enhanced expertise in AMBA protocols (AXI4, APB, AHB) and developed a System Verilog-based JTAG VIP for SOC stimulus delivery and post-silicon validation. -> Executed comprehensive verification of the DIMC Neural Processor SOC, including test planning, functional testing, and debugging across design hierarchies. -> Conducted power analysis and performance benchmarking for AI models using the emulation platform, optimizing digital NPU efficiency. -> Created a Python-based debugging tool for visualizing AHB/AXI transactions, reducing debug time and improving performance analysis. -> Spearheaded junior engineer teams, mentoring on complex verification projects and developing applications in Computer Vision and NLP for an application-level understanding.
STMicroelectronicsDesign Engineer
Jun. 2018 - Dec. 2020Project: SOC level verification of Neural Processor Unit IP for AI/ ML Applications (
https://blog.st.com/stm32n6/ ) -> Functional verification of Convolution Accelerator block of AI SOC comprising of Digital Neural Processing Unit and SRAM based In-Memory Compute. -> Created System Verilog coverage model for Convolution Accelerator block, conducted block-level
verification with C-based functional tests. -> Performed SOC integration tests, PLL bring-up, and debugged failed test cases. -> Created C based sample-accurate golden reference model for convolution accelerator present in NPU. -> Defined Memory BIST strategy, integrated it in SOC and performed BIST integration as well as functional tests. -> Performed Logic Synthesis of design, performed timing analysis at different PVT corners.
STMicroelectronicsIntern
Jan. 2018 - Jun. 2018Greater noida
Intch is a Professional Networking App for the Future of WorkSee more people like Akhilesh on Intch
300k+ people
130+ countries
AI matching
Get Intch if you'd like to
1026939 people
15
Business process lead @ Tata consultancy Services
212
AI Marketing Automation and Digital Strategist @ GV Shri
22
Founder @ Accession
74865 people
17
Senior QA Automation Engineer @ Luxoft
18
Founder & CEO @ GVM Technologies LLC
19
Data Engineer @ EY