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Work Background
amsOSRAM (via Chipright Ltd. Ireland)Verification Engineer
May. 2024 - Apr. 2025remoteIndependently handle complete verification of the core mixed signal module using a bottom-up approach
Created testbench (simulator/regression setup + connectivity) and verification environment for the digital top with several custom made UVCs (including register model and communication protocol)
Created testbench (simulator/regression setup + connectivity) and verification environment for the module top (digital + analog real number models) reusing the digital top environment
Improved design and documentation by reporting several issues
Debugged real number model netlist delivery
Participated in planning and effort estimation Created stand-alone testbench and UVC for top level JTAG interface
ANALOG DEVICES INTERNATIONAL IRELAND (via Chipright Ltd. Ireland)Verification Engineer
Apr. 2023 - Mar. 2024remoteImplement verification items to confirm correctness of RTL changes.
Update legacy testbenches to enable coverage collection
Create vPlan to follow verification progress
Debug and fix legacy failing testcases
Submit Jira tickets for outstanding issues
Create Confluence pages for documentation
INFINEON TECHNOLOGIES AUSTRIA (via HAYS AG)Verification Engineer
Feb. 2022 - Apr. 2023remoteCheck design fixes functionality and develop verification items to cover new requirements at top level using a UVM verification methodology.
Debug regression and investigate or fix issues.
Analyze functional and code coverage and implement items to fill holes
Apply coding rules and guidelines and contribute to code reviews
Generic target design examples: analog fault monitoring, design for test implementation, ADC result processing
Submit and track tickets for found issues (Agile) using Jira
ANALOG DEVICES INTERNATIONAL IRELAND (via Chipright Ltd. Ireland)Verification Engineer
May. 2021 - Jan. 2022remoteDevelop SV test cases to verify the top-level integration of specific features of SoCs
Delivered work packages in both mixed signal and digital oriented testbenches
Develop from scratch testbenches and UVCs for certain digital blocks to be re-used in the top level testbench
Generic target block examples: device core features like interrupt monitoring, communication protocols, register map etc.
Create the necessary verification elements to guarantee proper sign-off
Submit and track tickets for found issues
ams OSRAM via Chipright LtdMixed Signal Verification Engineer
Nov. 2020 - May. 2021remoteCreate or update simple SV real number models for analog blocks
Verify the basic functionality of the models and their corresponding schematic
Create reports with model vs schematic results
Build or update top level UVM tests targeted at mixed signal functionality
Create checkers and coverage to get verification closure
ANALOG DEVICES INTERNATIONAL, INC (via Chipright Ireland Ltd)Verification Engineer
Oct. 2017 - Nov. 2020remoteDeveloped SV test cases to verify in mixed signal the top level integration of
specific features of a large communication SoC
Developed UVCs for certain DSP digital blocks to be re-used in the top level
testbench
Infineon TechnologiesMixed Signal SoC Verification Engineer
Jul. 2010 - Nov. 2017Bucharest, RomaniaExperience with applying Digital Verification principles and Methodology to Mixed Signal Design.
Developed re-usable verification IP for analog / mixed signal functions.
Applied Metric-Driven Verification Methodology and UVM at SoC level with analog mixed signal simulations (not only real number models).
Set up the SoC verification framework.
Technical leading of a verification team.
Provided simulation set up support.
Proficient in UVM / mixed signal simulators. Behavioral Modeling position: Developed, verified, validated and delivered behavioral models for the division’s devices. Two types of delivered models depending of purpose: for external customers to aid in application design and simulation / for internal customers to aid in mixed signal verification or design.
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