Keep in touch with meI'm using Intch to connect with new people. Use this link to open chat with me via Intch app
Work Background
SiFivePrincipal Engineer
Oct. 2018San Mateo, CABuilding future HDL IR and compiler infrastructure github.com/llvm/circt. Developed format for capturing integration intent with reusable IP blocks, models, interfaces, registers; and SoC tools: github.com/sifive/duh. Developed DSP library, code generation and profiling tools for RISC-V Vector processor. Work in RISC-V foundation technical groups.
Signal Laboratories, Inc.Principal Engineer
Jan. 2018 - Oct. 2018Menlo Park, CAArchitecture, design and RTL implementation of wireless baseband processor based on RISC-V architecture and custom instruction extensions; coarse grain reconfigurable systolic datapath optimized for complex DSP workload. Development of new distributed MIMO multicarrier wireless PHY algorithms, implementation in GnuRadio, Octave, C, ASM. RF design and prototyping including antennas and helical filters.
ArterisSW Director, Principal Engineer
Apr. 2014 - Jan. 2018Campbell, CALeading software development team in design of configuration and generation tool for heterogeneous cache coherent SoC interconnect IP. Development of customer facing Web UI, tools and libraries. Developed new high-level Hardware Description Language, compiler and tools. NoC performance modeling framework in C++.
Intel CorporationSenior Design Engineer
Oct. 2011 - Apr. 2014Santa Clara, CADevelopment of VLSI Soft-IP collateral, configuration / generation software (TCL, Perl) for several configurable SoC infrastructure / fabric IPs. Was responsible on architecture and Verilog RTL design of custom external memory interface. Feature enhancements and porting of several Verilog / VHDL RTL blocks for new multi-standard, mixed signal wireless IC. Perl scripting / automation of design and documentation flows.
Intel Corporation, Digital Home GroupSystems Architect
Jun. 2008 - Oct. 2011Chandler, AZCustom base-band DSP processor extended with elastic re-configurable systolic array technology:
- Technical leadership;
- Architecture, instruction set specification / design;
- Design-time development and processor generation software tools (Perl);
- C++ firmware development, compiler tools architecture; Frequency domain ATSC demodulator:
- Leadership through research, algorithm, MATLAB model development and performance evaluation / optimization.
Intel Labs, Wireless Communications LabSoC Architect
Apr. 2006 - May. 2008St.Petersburg, RussiaArchitected design-time configurable, run-time programmable / reconfigurable array data-streaming machine IP for multi radio based SoCs.
- Author micro-architecture specifications
- Ensure systems requirements are met
- Analyze applications and incorporate key technologies and standards
- Technical leadership of RTL design, compiler tool-chain and application development teams to perform joint optimization of the complexity / programmability trade-offs involving hardware / software partitioning
- SoC power efficiency architecture exploration research
Intel Labs, Wireless Communications LabSenior VLSI Design Engineer
Mar. 2005 - Mar. 2006St.Petersburg, RussiaProgrammable OFDM specific DSP engine:
- Architecture definition
- Verilog RTL design
- Simulation, synthesis, SystemVerilog functional verification, FPGA prototyping
- IEEE802.11a protocol porting
Intel Corporation, Intel Communications GroupSenior Hardware Engineer
Aug. 2003 - Jan. 2005Nizhny Novgorod, RussiaBuilding SoC design / verification productivity system for Broadband Wireless IEEE 802.16 (WiMAX) project:
- Pre-silicon chip validation environment, and tools development
- Build custom Multi-FPGA full chip prototyping platform
- Embedded DSP processor microarchitecture optimizations
NEOTEC Semiconductor Ltd.Digital IC Designer
Apr. 2001 - Jun. 2003Chu Pei, TaiwanARM based embedded multimedia platform SoC project:
- Visual Multi Processor Unit with LCD controller and graphic acceleration functions
- Integrated memory subsystem
- Peripheral Processor Unit with SD MMC card functions
- System and processor architecture, Verilog RTL, logic synthesis, static timing analysis, FPGA prototyping and performance analysis, Forth firmware development
- Work as Project Manager in building up an corporative IP reuse and documentation infrastructure
Telecommunication Company of Molodechno (MTK)Head of design group
Aug. 1997 - Mar. 2001Molodechno, BelarusEmbedded system development
- Schematic, Verilog RTL, telecommunication and voice application firmware
- System and embedded 16-bit stack processor architecture, FPGA implementation
- Russian mobile phone systems: "Kart", "Altai", "VoLeMoT", "Vilia" protocol, schematic, PCB, hardware and software implementation
Laboratory of New Technologies (NTL)Application Engineer
May. 1996 - Jun. 1997Minsk, BelarusEngaged in development of new Stack microprocessor, testing, benchmarking of DSP algorithms, architecture documentation. Developing Forth compiler, library and applications.
Radioplant "Sputnik", R&D CenterElectronic designer
Aug. 1994 - Aug. 1996Molodechno, BelarusI developed the schematic and Forth firmware for the new mobile phone station using the stack processor. Implementation of radio modem and voice processing algorithms. Result: additional consumer functions, serial production at the plant, BOM cost reduction
Intch is a Professional Networking App for the Future of WorkSee more people like Aliaksei on Intch
300k+ people
130+ countries
AI matching
Get Intch if you'd like to
265253 people
16
Marketing Consultant @ Out West Agency
15
CEO & Founder @ Dena Patton coaching and training
16
Software Engineer @ Sasqnet
66915 people
16
Marketing Consultant @ Out West Agency
15
COO @ eye Safe T/A Vert
15
Brand Strategist & CEO, Founder @ Backroom