SynopsysR&D Engineer II
Sep. 2011 - Jun. 2014Армения• Leading project design team in defining initial floor plan, block placement, number of required routing layers, power grid planning, the layout of IC blocks (level shifters, operation amplifiers, voltage regulators, PLL, frequency synthesizers, RX and TX)
• Developing IC layout from scratch by using a CAD tool for physical verification
• Performing electrical characteristics: electromigration and IR drop verification and amendment of the designed layout Designed Interface IP (USB2.0 USB3.0 HSIC SATA DDR3) on advanced nodes (45/40nm; 32/28nm; 20nm; 16/14nm and I/Os, ESD blocks of different foundries